1. Field of the Invention
The present invention relates to a stacked semiconductor device and, more specifically, to a stacked semiconductor device comprising a plurality of stacked layers of semiconductor elements and having high quality.
2. Description of the Prior Art
Recently, trials have been made to manufacture a versatile stacked semiconductor device having a plurality of circuit elements stacked in layers in a three-dimensional structure, namely, a so-called three-dimensional circuit device, having an increased component mounting density and diversified functions. In one proposed process of manufacturing a stacked semiconductor device, an insulating layer is formed over a previously formed circuit element, a polycrystalline or amorphous semiconductor layer is formed over the insulating layer, only the semiconductor layer is heated and melted by irradiating the semiconductor layer by an energy beam such as a laser beam to change the polycrystalline or amorphous semiconductor layer into a single crystal semiconductor layer, and then circuit elements are formed in the single crystal semiconductor layer.
FIGS. 1A through 1G are sectional views of assistance in explaining processes of a conventional stacked semiconductor device manufacturing method. In FIG. 1A, indicated at 1 is a single crystal silicon substrate having a principal plane of [100] or silicon substrate having a principal plane of [100] crystallographically equivalent to the former. A circuit element (MOS transistor) A formed in the first layer through an ordinary MOS transistor manufacturing method comprises an oxide film 21, a gate electrode 3, and a source-drain line 4, which is formed of a metal silicide having a high melting point, such as tungsten silicide, which withstands a high-temperature process for stacking. After the circuit element A has been formed in the first layer, an oxide film 22 serving as a first layer insulating film is formed over the first layer by a chemical vapor deposition method (hereinafter referred to as "CVD method"), a resist film is formed over the oxide film 22, and then the surface of the resist film is smoothed by an etch back process. Then a square first opening 5 having sides of 3 .mu.m is formed through the oxide film 22 as a seed to form a single crystal silicon layer having the same crystal axis as the single crystal silicon substrate over the first oxide film 22.
Then, as shown in FIG. 1B, a single crystal silicon layer (hereinafter referred to as "first epitaxial silicon layer") 6 having the same crystal axis as the single crystal silicon substrate 1 is grown by a selective epitaxial process, and then a first polycrystalline silicon film 7 of 0.5 .mu.m in thickness is formed over the entire surface of the oxide film 22 by a CVD method, as shown in FIG. 1C.
Then, as shown in FIG. 1C, the first polycrystalline silicon layer 7 is irradiated by an argon laser beam 8 of 100 .mu.m in diameter by moving the spot of the argon laser beam 8 in the direction of an arrow at a scanning speed of 25 cm/sec. The first polycrystalline silicon layer 7 is melted by the argon laser beam 8 in a molten silicon 72 which solidifies and recrystallizes after the completion of irradiation by the argon laser beam 8. Lateral epitaxial growth starts from the first epitaxial silicon layer 6 serving as a seed during the solidifcation of the molten silicon 72, and thereby the first polycrystalline silicon layer 7 formed over the oxide film 22 changes into a first single crystal layer 71 having the same crystal axis as the single crystal silicon substrate 1. Methods of forming a single crystal semiconductor layer over an oxide film by means of a laser beam are described in detail in U.S. patent application Ser. Nos. 022,717 and 022,402, both filed Mar. 6, 1987.
Then, as shown in FIG. 1D, the first single crystal silicon layer 71 is etched by a photographic eteching process to form a single crystal silicon layer 74 for forming a MOS transistor therein, and to form a single crystal silicon layer 73 to be used as a seed over the epitaxial silicon layer 6.
Then, as shown in FIG. 1E, a second circuit element (MOS transistor) b is formed on the single crystal silicon layer 74 by the same process as that for forming the first MOS transistor A. Shown in FIG. 1E are an oxide film 23, a gate electrode 31, and a source-drain line 41. The source-drain line 41, similarly to the source-drain line 4 of the first circuit element A, is formed of a metal silicide having a high melting point.
A shown in FIG. 1F, after the second circuit element B has been formed, a second oxide film (second layer insulating layer) 24 is formed by a CVD method, the second layer insulating layer 24 is coated with a resist film, and then the surface of the resist film is smoothed by an etch back process. A second opening 50 is formed in the second oxide film 24 in a portion corresponding to the second single crystal silicon layer 73, a second epitaxial silicon layer 61 is grown in the second opening 50, similarly to the first epitaxial silicon layer 6, by a selective epitaxial growth process, a second polycrystalline silicon layer, not shown, is formed over the entire surface of the planarized second oxide film 24 and the single crystal silicon layer 73 by a CVD method, and then the second polycrystalline silicon layer is irradiated by a laser beam to change the second polycrystalline silicon layer into a second crystal silicon layer 75.
Then, as shown in FIG. 1G, the second single crystal silicon layer 75 is etched in a desired pattern in the same manner as that for forming the first and second layers, and a gate electrode 301, an oxide film 203, and a source-drain line 401 formed of a metal silicide having a high melting point are formed over the second single crystal silicon layer 75 to construct a third circuit element (MOS transistor) C. thus a three-layer three-dimensional circuit device is fabricated.
In the conventional stacked semiconductor device manufacturing method, the second epitaxial silicon layer 61 is used as a seed to change the second polycrystalline silicon layer into the second single crystal silicon layer 75 having the same crystal axis as the single crystal silicon substrate 1. However, since the second epitaxial silicon layer 61 is connected through the single crystal silicon layer 73 to the first epitaxial silicon layer 6, and the thermal conductivity of the silicon is greater than that of the oxide film, heat is transferred through the second epitaxial silicon layer 61, the single crystal silicon layer 73 and the first epitaxial silicon layer 6 to the single crystal silicon substrate 1 in irradiating the second polycrystalline silicon layer by a laser beam to change the second polycrystalline silicon layer into the single crystal silicon layer. Consequently, the temperature of the second polycrystalline silicon layer is able to rise only slightly and the second polycrystalline silicon layer is unable to melt, and hence lateral epitaxial growth does not occur. Accordingly, such a conventional stacked semiconductor device has a problem that the electrical characteristics of the third circuit element C are very inferior. Methods have been proposed to solve such a problem, in which the diameter of the second opening 50 for forming the second epitaxial silicon layer 61 is reduced to a diameter on the order of 2 .mu.m or an antireflection film capable of preventing the reflection of the laser beam is formed over the second epitaxial silicon layer 61. However, in those methods, the second polycrystalline silicon layer formed over the second epitaxial silicon layer 61 is unable to melt.
When the opening for changing the polycrystalline silicon layer into the second single crystal silicon layer 75 having the same crystal axis as the single crystal silicon substrate 1 to form the third circuit element C is formed directly above the opening 5 for the second circuit element B, the temperature of the polycrystalline silicon formed in the opening rises only slightly and the polycrystalline silicon does not melt and hence the lateral epitaxial growth does not occur, because the thermal conductivity of silicon is greater than the oxide film.
Furthermore, such phenomena become more and more remarkable with increase in the thickness of the layer insulating film, and hence it has been impossible to melt the polycrystalline silicon formed in the opening in recrystallizing the polycrystalline silicon layer to form the third layer. To solve such a problem a trial has been made, in which the size of the opening is reduced to suppress heat conduction. However, the size of the opening must be 0.5 .mu.m or below to enable the polycrystalline silicon to melt in the opening, which entails problem in the reliability of the process for forming the opening.